(1) Field of the Invention
This invention relates to methods of preserving alignment marks in integrated circuit substrates and more particularly to preserving alignment marks in methods using shallow trench isolation and chemical mechanical polishing.
(2) Description of the Related Art
U.S. Pat. No. 5,401,691 to Caldwell describes a method of forming an alignment mark during semiconductor device manufacturing. The method uses a first area and a second area provided on a semiconductor substrate with the first area adjacent to the second area. The invention describes the formation of an alignment mark using an inverse open frame.
U.S. Pat. No. 5,310,691 to Suda describes the formation of a concave or convex step formed on the surface of the epitaxial layer in a boundary between the memory cell region of an integrated circuit element and the peripheral circuit region of the integrated circuit element. The concave or convex step is used as an alignment mark in a later processing step.
U.S. Pat. No. 5,229,316 to Lee et al. describes a method of forming isolation trenches to provide device isolation in integrated circuit elements.
A Patent Application TSMC-97-265 Ser. No. 09/067,262; Filed Apr. 27, 1998, pending; entitled "METHOD OF PHOTO ALIGNMENT FOR SHALLOW TRENCH ISOLATION WITH CHEMICAL MECHANICAL POLISHING" and assigned to the same assignee describes methods of preserving alignment marks in integrated circuit substrates.